Design Parallel in serial out shift Register using VHDL language

--here the logic to design parallel in serial out using vhdl


library IEEE;
use  IEEE.STD_LOGIC_1164.ALL;
use  ieee.std_logic_unsigned.all ;
use  ieee.std_logic_arith.all


entity PISO_behav is
    Port ( clk,reset : in  STD_LOGIC;
           datain : in  STD_LOGIC_VECTOR (3 downto 0);
           dataout : out  STD_LOGIC);
end PISO_behav;

architecture Behavioral of PISO_behav is
signal datain1 : std_logic_vector(3 downto 0);
signal int : integer range 0 to 3 ;
begin
process(clk,reset,int,datain)
begin
if(reset ='0') then
datain1 <= datain ;
int <=1 ;
elsif rising_edge(clk) then
  int <= int  +1 ;
if(int = 4) then
datain1 <= datain ;
int <=0;
else 
  datain1(2) <= datain1(3) ;
   datain1(1) <= datain1(2) ;
   datain1(0) <= datain1(1) ; --another logic is here
  datain1(3) <= datain1(0) ;    --datain1 <= datain(3) & datain1(3 downto 1) ;--& datain(3) ;
   end if ;
end if ;
end process ;
   dataout <= datain1(0);  
end Behavioral;