Design Parallel in serial out shift Register using VHDL language

--here the logic to design parallel in serial out using vhdl


library IEEE;
use  IEEE.STD_LOGIC_1164.ALL;
use  ieee.std_logic_unsigned.all ;
use  ieee.std_logic_arith.all


entity PISO_behav is
    Port ( clk,reset : in  STD_LOGIC;
           datain : in  STD_LOGIC_VECTOR (3 downto 0);
           dataout : out  STD_LOGIC);
end PISO_behav;

architecture Behavioral of PISO_behav is
signal datain1 : std_logic_vector(3 downto 0);
signal int : integer range 0 to 3 ;
begin
process(clk,reset,int,datain)
begin
if(reset ='0') then
datain1 <= datain ;
int <=1 ;
elsif rising_edge(clk) then
  int <= int  +1 ;
if(int = 4) then
datain1 <= datain ;
int <=0;
else 
  datain1(2) <= datain1(3) ;
   datain1(1) <= datain1(2) ;
   datain1(0) <= datain1(1) ; --another logic is here
  datain1(3) <= datain1(0) ;    --datain1 <= datain(3) & datain1(3 downto 1) ;--& datain(3) ;
   end if ;
end if ;
end process ;
   dataout <= datain1(0);  
end Behavioral;

Design Finite State Machine Using VHDL programming Language

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: NIlesh THAKUR
-- 
-- Create Date:    12:45:12 11/09/2014 
-- Design Name: 
-- Module Name:    finite_state - Behavioral 
-- Project Name: 
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; --header files
use ieee.std_logic_unsigned.all --header file

entity finite_state is   --Entity
    Port (
           clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           toggle : in  STD_LOGIC;
           output : out  STD_LOGIC
         );
end finite_state;

architecture Behavioral of finite_state is

type state_type is (st0,st1);  --define states

signal pstate, nstate : state_type;
begin
     process(clk,reset)
     begin
          if(reset ='1') then
             pstate<=st0;
       elsif rising_edge(clk) then
          pstate <= nstate;
       end if;
  end process;

 process(pstate,toggle)
 begin
 --output <='0';
     case pstate is
       when st0=>
          output <= '0';
       if (toggle ='1') then
        nstate <=st1;
       else
        nstate <= st0;
       end if;
     when st1=>
       output <='1';
       if(toggle='1') then
         nstate <=st0;
       else
         nstate<=st1;
       end if;
     when others=>
        output<='0';
        nstate <= st0;
   end case;
 end process;

end Behavioral;