Steps to write VHDL code in
XILINX ISE WebPack
Here are the steps to write
a VHDL code in behavioural modelling style using Xilinx web pack version.
First visit Xilinx official
website and download fresh copy of XILINX ISE design suite Web Pack version.
It’s a freeware for student choose code limit version.
After download Xilinx ISE
install it in C drive and open it.
Here is your first Program.
Step 1:-
Click on new project
Step 3:-Click on next button
next window is project settings now don’t do anything click on next button and
then finish button.
After click on finish button
this window will open
Step 4:- after click on new
source file this window will open
Step 5 :- when you click on
next button a new window will open where you have to enter input output
variable for example
If you are designing and
gate then you have 2 inputs and 1 output
Step6:- Click on next button
next window will open with your file where you can write your vhdl program here
I attached next snapshot of that.
Step 7:- here is your AND gate program when there is no
syntax error click on implement design and then check simulation of your
program.
