Design Finite State Machine Using VHDL programming Language

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-- Company: 
-- Engineer: NIlesh THAKUR
-- 
-- Create Date:    12:45:12 11/09/2014 
-- Design Name: 
-- Module Name:    finite_state - Behavioral 
-- Project Name: 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL; --header files
use ieee.std_logic_unsigned.all --header file

entity finite_state is   --Entity
    Port (
           clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           toggle : in  STD_LOGIC;
           output : out  STD_LOGIC
         );
end finite_state;

architecture Behavioral of finite_state is

type state_type is (st0,st1);  --define states

signal pstate, nstate : state_type;
begin
     process(clk,reset)
     begin
          if(reset ='1') then
             pstate<=st0;
       elsif rising_edge(clk) then
          pstate <= nstate;
       end if;
  end process;

 process(pstate,toggle)
 begin
 --output <='0';
     case pstate is
       when st0=>
          output <= '0';
       if (toggle ='1') then
        nstate <=st1;
       else
        nstate <= st0;
       end if;
     when st1=>
       output <='1';
       if(toggle='1') then
         nstate <=st0;
       else
         nstate<=st1;
       end if;
     when others=>
        output<='0';
        nstate <= st0;
   end case;
 end process;

end Behavioral;